Intro to Verilog

ucla | CS M152A | 2023-04-03T12:24

Definitions

hardware design language (HDL)
used to compile on FPGA boards
module based design (combinational and sequential logic)
i.e. we write in boolean algebra
- e.g. O = ~(A&B C) → O = NOT( A AND B OR C)
work with wires not variables
- previous example O is a wire
cant remove virtual modules (in verilog) because they represent hardware (physical modules on FPGA board)

Wires
- I/O signals for modules
- cant set wires to values i.e. not a variable
- states: 1, 0, X (undefined/don’t cares)
Registers
- hardware component - has memory “keeper”
- stores values (a sequence of flip flops)
Parameters (constants)

always block - runs on loop (parallel)

  always @* //can only set registers
  		c = a + b; //adder

assign block - wires
Cannot be placed inside always blocks
```
  assign c = a + b; //only for wires
```
initial - runs once
To set initial values to registers
NEVER use variables (NO for/while loops)

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**SUMMARY
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