1 - Intro to Computer Architecture

ucla | CS M151B | 2024-01-09 17:21

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Table of Contents

• CPU Time
• Denard’s (MOSFET) Scaling
• Power Wall
• Memory Wall

CPU Time

• CPI = Clock per instructions \(\text{CPU Time}=\frac{\text{Instruction Count}\times\text{CPI}}{\text{Clock Rate}}=IC\times CPI\times\text{Clock Time}\)
• Clock Frequency/Rate\(\text{Clock Rate}=\frac{1}{\text{Clock Time}}\)

Denard’s (MOSFET) Scaling

• as transistors get smaller, capacitance and voltage reduce
• then should be possible to increase (we don’t increase it is just a result of the equation) frequency if power is the same
• higher frequency means higher clock/performance
• where alpha is transistor switching rate \(Power=\alpha\cdot CFV^2\)

Power Wall

• quantum tunneling of electrons of transistors becoming too small
• comes from Denard’s scaling
• solutions come from introducing more ores/making dies bigger at the same transistor size

Memory Wall

• the gap between cpu performance at a transistor level (following Moore’s doubling law) vs memory performance increase rate (linear)