17 - FPGAs

ucla | CS M151B | 2024-03-07 16:14

---

Table of Contents

• Lookup Tables
  • Registers
  • DSP blocks
  • Memory
• Memory Interconnect
  • Zynq Interface
  • AXI Protocol

Lookup Tables

• all combinational circuits are truth table
• we make LUTs by optimizing TTs by having some number of inputs and some number of outputs (like a mux):
• thus sequential logic made by attaching a flip flop
• then the combinational must choose which FF to activate using a MUX e.g., regs

  Registers

  

• we use island structure:

  DSP blocks

• bc fpgas are slow at arithmetic, we include dediated DSPs:

  Memory

  

Memory Interconnect

• because mosst boards are FPGA+arm cpu, there needs to b e a memory interconnect

  Zynq Interface

  

  AXI Protocol

• Master-slave interconnect:
  • 
• done as a 4-burst handshake: