7 - RISC-V Circuitry

ucla | CS M151B | 2024-01-30 17:23

Table of Contents

Instructions

  • Reduced ISA
  • Implementation

    • Datapath

  • basic datapath

    Next PC Calc

  • Reg File

  • Branching

  • Memory Path

  • CPU Path

  • opcodes sent to control logic -> output to mux select and reg select

    OP Decoding

  • ALU ops